Tie the outputs of the counter to the LEDs.# Returns: 6:10 PM add_time( "11:30 AM", "2:32", "Monday") Thus, we get a counter that increases every second. In the wrapper, we can use the output of this clock divider to provide the clock signal for the 8-bit counter we designed in Step 1. Now that we have a counter that increases by 1 when the clock rising edge arrives and a clock divider that can provide a clock signal that is exactly 1 Hz, we can now write a wrapper module. Reg count always (posedge (clk ), posedge (rst ) ) begin if (rst = 1 'b1 )Ĭount <= 32 'b0 else if (count = constantNumber - 1 )ĭescribe the flip-flop together with the comparator as follows:Īlways (posedge (clk ), posedge (rst ) ) begin if (rst = 1 'b1 )Ĭlk_div <= 1 'b0 else if (count = constNumber - 1 ) Now we will start to describe the circuit:Ĭreate a Verilog module for clock divider.ĭefine the constant as a local parameter: So the constant we need to choose here is 50000000. In another words, it takes 50000000 clock cycles for clk_div to flip its value. So it should take 100000000 clock cycles before clk_div goes to '1' and returns to '0'. As an example, the input clock frequency of the Nexys3 is 100 MHz. First, we will need to calculate the constant. In this example, we are going to use this clock divider to implement a signal of exactly 1 Hz frequency. As a result, the frequency of clk_div is one sixth of the frequency of original clk. So it takes 6 clock cycles before clk_div goes to 1 and returns to 0 again. When it reaches 3 again, clk_div turns back to 0. It takes another three cycles before the output of the counter equals the pre-defined constant, 3. When it reaches 3, the output of clock divider (clk_div) turns to 1, and the counter resets itself. It takes three clock cycles before the output of the counter equals the pre-defined constant, 3. Let's assume that the pre-defined number is 3, and the output of clock divider (clk_div) is initialized to 0. When EQ is asserted, the output of the clock divider flips. The comparator compares the output of the counter with the pre-defined constant and asserts EQ if the output of counter is equal to the pre-defined constant. It also resets its output to '0' when it reaches the constant number defined in the constant block. In the block diagram, the counter increases by 1 whenever the rising edge of clk arrives. The block diagram of such a clock divider is shown in Fig. In this section, we can use a counter with a comparator to condition a flip-flop with an inverter to implement a clock divider that can control the output frequency more precisely. In the previous project, we explained how to use a flip-flop with an inverter to implement a clock divider that divides the frequency in half. Q <= 8 'b0 else // How Output reacts when Rising Edge of Clock Arrives ? ) always (posedge (clk ), posedge (rst ) ) // When will Always Block Be Triggeredīegin if (rst = 1 'b1 ) // How Output reacts when Reset Is Asserted So, the code for a counter is shown as follows: How does output react when the rising edge of clock arrives? The output is updated to the output of the adder, which is the output of the counter before the rising edge arrives, plus 1. How does output react when reset is asserted? The output of the counter will be reset to '0' when reset is asserted. When will the always block be triggered? The output of the counter will be updated at the rising edge of the clock (functionality of FF) or the rising edge of the reset signal (asynchronous reset). To implement the counter behaviorally, there are three statements we need to make: To describe any sequential circuit, we can use the similar always block as the one we used to describe a D flip-flop. Actually, it is a lot easier to code it behaviorally. To describe the circuit structurally in Verilog, you can use the RCA and the flip-flops you implemented in previous projects. As a result of the analysis, the flip-flops provide a timing reference (clock) to the adder so that the output of the counter is increased by 1 every time the rising edge of clock arrives. After the second rising edge of the clock arrives, 2 will show up on the outputs of the counter. And 1+1=2 will be presented at the inputs of the flip-flops. When the reset signal is de-asserted, the outputs turn to 1 after the rising edge of the clock arrives. The outputs of flip-flops feed back to the input of the ripple-carry adder and present 0+1=1 at the input of the flip-flops. When reset signal “rst” is asserted, the outputs of the counter (Q) are 0. The block diagram of a counter is shown below in Fig. USB Scopes, Analyzers and Signal GeneratorsĪ counter is no more than an adder with a flip-flop for each of the output bits.
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